Today sees the announcement from Synopsys, Inc., over their newest technology and solutions for chip designers. As an industry first, the company has released their newest HBM3 IP solutions, consisting of PHY, controller and IP for verification of 2.5D multi-die packages. This technology will further increase the development of minimal power and high-bandwidth specifications for SoC architectures aimed at efficient and high-processing AI, computing, and applications for graphics.
Synopsys’ DesignWare controller and IP pushes “high memory bandwidth at up to 921 GB/s.” A first for the chip industry, Synopsys Verification IP and solution utilizes coverage internally as well as verification standards, HBM3 memory options for ZeBu emulators (off-the-shelf), and a unique HAPS prototype design for their systems to verify information from HMB3 IP to system-on-chips. The company increases developments for their HBM3 designs, causing the 3DIC Compiler platform for multi-die use for a “fully integrated architectural exploration, implementation and system-level analysis solution.”
Synopsys DesignWare HBM3 PHY IP is a 5-nm process, and is available as pre-made or customer configurable PHY, operating at speeds of 7200 Mbps per pin pn chip, improving efficiency of power and supports as high as “four active operating states,” allowing for dynamic scaling frequencies. DesignWare uses an micro bump array that is optomized to assist in minimizing the area. Support for the interposer trace lengths allows manufacturers more room in PHY placements to not have it impact its performance.
—John Koeter, Synopsys Senior Vice President of Marketing and Strategy for IP
Source: TechPowerUp, Synopsys
